FIG. 1 schematically shows a conventional ROM structure. It includes a plurality of memory cells 10 arranged in rows and columns. The cells 10 of each row are selected by a respective word line W, and a selected cell presents its data on a bit line BL common to the cells of the same column. An address decoder, not shown, controls word lines W according to the read address presented to the memory.
Each bit line BL is connected to a high supply potential Vdd via a respective P-channel MOS precharge transistor MP. All precharge transistors MP are controlled by a common precharge line P.
Further, bit lines BL are connected to read amplifiers 12. Generally, the bit lines are grouped in several sets, each set being associated with a single sense amplifier 12 via a multiplexer 14. Each multiplexer 14 selects the bit line to be connected to the amplifier according to the read address presented to the memory.
As shown, the programmed cells 10 include an N-channel MOS transistor MN connected between the corresponding bit line and the low supply potential, while the unprogrammed cells 10 include no transistor. The transistors MN of the cells of a same row are all controlled by the corresponding word line W.
Generally, read amplifiers 12 are comparators that compare the outputs of the corresponding multiplexers 14 with a reference value Vref sampled on a reference bit line DBL. Reference bit line DBL corresponds to a column in which all cells are programmed. Like a normal bit line, reference bit line DBL is connected to high potential Vdd by a precharge transistor MP controlled in the same way as all other precharge transistors MP.
The elements forming the reference column are chosen so that reference bit line DBL discharges slower, during a reading, than a normal bit line BL. For this purpose, for example, the transistors forming the cells of the reference column are smaller, or less conductive, than the transistors of the cells forming the normal columns.
As illustrated to the left of FIG. 1, precharge line P is controlled in phase with the word line W selected by the address decoder. When lines P and W are low, the row is not selected and all bit lines BL and DBL are drawn to potential Vdd by transistors MP.
When lines P and W switch high, the precharge transistors MP are off while the transistors MN of the selected row are turned on and discharge their respective bit lines BL and DBL. Reference bit line DBL discharges slower than a normal bit line. Thus, the level difference between the reference bit line and a normal bit line being discharged increases and reaches a sufficient value to switch a sense amplifier 12 to a high state. The level difference between reference bit line DBL and a bit line BL that has not discharged increases in the opposite direction and reaches a value causing the switching of a sense amplifier to a low state.
A disadvantage of the ROM of FIG. 1 is that, for each read cycle, the bit lines undergo significant charge variations. Indeed, they are initially charged to Vdd to be discharged to a practically null value. This charge variation results in a high dynamic consumption proportional to the memory read frequency.
Further, in the quiescent state, precharge transistors MP are on. Although transistors MN of the memory cells are off, they exhibit a leakage current causing a static consumption. This leakage current tends to increase with new technologies due to the fact that transistors become smaller and smaller.